1. Field of the Invention
The present invention relates to asynchronous data processing apparatus, and in particular to techniques for enabling asynchronous data processing apparatus to operate in a power efficient manner.
2. Background of the Prior Art
Data processing apparatus, such as a microprocessor, will typically be implemented using a synchronous architecture, since this is generally considered to be less complex than an asynchronous architecture. Synchronous microprocessors operate under the control of an externally supplied clock signal, whereas asynchronous microprocessors need to be self-timed and to operate without any externally supplied clock. The absence of an externally supplied clock increases the complexity in designing a microprocessor. For example, the designer has to consider how the flow of data is to be controlled in the absence of any reference clock, and the delays of processing elements must be measured by the circuit itself instead of being simply modelled by the clock period.
However, microprocessors based on synchronous designs are not particularly power efficient. The clock in a synchronous circuit runs all the time, causing transitions in the circuit that dissipate electrical power. The clock frequency must be set so that the processor can cope with the peak workload and, although the clock rate can be adjusted under software control to varying demands, this can only be done relatively crudely at a coarse granularity. Therefore most of the time the clock is running faster than is necessary to support the current workload, resulting in wasted power.
Hence, an object of the present invention is to provide a microprocessor with an improved power efficiency.